This invention relates generally to semiconductor processing, and in particular to contact and via holes. More specifically, the invention relates to a method of reducing gate oxide damage due to radio frequency (RF) sputter cleaning of high aspect ratio contact and via holes.
In semiconductor processing, conductive elements in non-successive layers of the semiconductor wafer may be connected by contacts or vias. A via is a connection between two metallic features in different layers of a semiconductor wafer (a "vertical" connection). A contact is a connection between metallic and non-metal conducting or semiconducting (such as silicon, polysilicon, or silicide) features in different layers of a semiconductor wafer.
A contact or via is typically formed by depositing a conductive material in a hole etched through a layer of dielectric between the two layers to be connected (an inter-layer dielectric ("ILD"). An example of a typical process for forming a contact is shown in FIGS. 1A-D. FIG. 1A shows a portion of a semiconductor wafer 100 having a feature in a semiconductor layer 102, for example a polysilicon floating gate, covered by an ILD 104, for example silicon dioxide (SiO.sub.2). FIG. 1B shows a contact hole 106 etched in the ILD 104, for instance by plasma etching or reactive ion etching (RIE), using conditions well known in the art. Such a hole typically has a high aspect ratio, for example a depth twice its diameter or width (2:1 aspect ratio). A typical via hole in a 0.35 .mu.m semiconductor device size environment may be about 500 to 1000 nm deep by about 200 to 500 nm in diameter.
In order to provide the best possible connection to the semiconductor layer 102, the contact hole 106 is then typically subjected to a cleaning procedure to remove the native oxide which forms on the semiconductor layer 102 and any polymer residue remaining from the etch chemistry which forms the hole 106. This cleaning is typically accomplished by a wet etch process whereby a selectively corrosive liquid, such as hydrofluoric acid (HF) is dispensed into the hole and then removed. The cleaned contact hole 106 may be coated with a deposited liner material 110, such as tungsten nitride (WN), titanium nitride (TiN) or titanium tungsten (TiW). The liner material 110 is typically anisotropically deposited, for example, by physical vapor deposition (PVD). The liner 110 provides a good base for deposition of a metal plug 108, typically tungsten (W), deposited by chemical vapor deposition (CVD), as shown in FIG. 1C. It also provides a barrier to prevent corrosion or diffusion of metal ions from the contact or via metal plug 108 into the layer to be connected 102.
Next, the wafer surface is typically planarized, for instance by chemical mechanical polishing (CMP), before a metal layer 112, typically aluminum or an aluminum alloy, such as aluminum copper (AlCu), is deposited over the ILD 104 and plug 108 and patterned, as shown in FIG. 1D. The plug 108 provides an electrical connection (contact) between the semiconductor layer 102 and the metal layer 112 through the ILD 104. Such a process is also applicable to the formation of vias where both layers being connected are metallic.
FIG. 2 depicts a portion of a conventional semiconductor wafer showing an example of the context in which contacts and vias may be used. The wafer 200 includes a semiconductor substrate 202, typically composed of single crystal silicon (Si). The top of the substrate 202 includes doped CMOS transistor source 204 and drain 206 regions separated by a gate oxide 208 region, usually about 35 to 100 .ANG. in thickness. The transistor gate 210, typically composed of doped polysilicon, is deposited above the gate oxide 208. The particular transistor shown in FIG. 2 was formed using a silicide process, such as are well known in the art. Silicide (e.g., WSi, TiSi.sub.2 or CoSi.sub.2) layers 212, 214 and 216 cover the source 204, drain 206, and gate 210 regions, respectively, to improve their conductivity. Spacers 218 separate the gate 210 for the source 204 and drain 206 to prevent shorts.
The transistor region is covered by a first layer of ILD 220, on which a first metal layer 230 is deposited and patterned. The first metal layer 230 and floating gate 210, 216 are connected by a contact 225 (including liner 226). The first metal layer is in turn covered by a second layer of ILD 240 (also referred to as inter metal dielectric ("IMD") where the dielectric separates two metal layers), on which a second metal layer 250 is deposited and patterned. The first 230 and second 250 metal layers are connected by a via 235 (including liner 236).
Attention has recently been given to the improvement of the process of cleaning contact or via holes prior to deposition of contact and via materials in order to minimize contact and via resistance. Conventional wet etch cleaning processes have drawbacks including that the etching liquid does not always reach the base of the high aspect ratio contact and via holes, and even when it does, it is not always successful in removing contaminants from the holes. Another way to clean contact and via holes, which appears to provide improved results is radio frequency (RF) sputtering. However, plasma induced gate oxide damage may result form such conventional RF sputtering.
FIG. 3 shows a portion of a semiconductor wafer 300 having a substrate 301, a gate oxide layer 302, a polysilicon gate layer 303, an ILD layer 304, and a contact hole 306. In RF sputtering, the wafer 300 may be biased to a low potential, for example about -50 to -500 V (typically about -200 V) while a high voltage plasma of argon ions (Ar.sup.+) 310 and electrons 312 is produced by treating argon gas with RF energy above the wafer surface. The following RF process conditions are typically used: the power may range from about 20 to 700 W; the argon pressure may range from about 0.05 mtorr to 25 mtorr; the etch time may range from about 0.5 to 100 s.
The argon ions 310 and electrons 312 from the plasma produced by the RF energy are drawn into the hole 306 by the low potential. The electrons 312 tend to move randomly, while the argon ions 310 move more directionally. As a result, a non-uniformity tends to develop in the plasma as the top portion 308 of the hole 306 and the wafer surface 305 surrounding the hole 306 become negatively charged by the impact of electrons 312. The electrical field due to this negative charge produces an electron shadowing effect whereby electrons 312 subsequently moving in the direction of the hole 306 are repelled. Thus, the number of electrons 312 reaching the bottom 307 of the hole 306 is greatly reduced. Meanwhile, a much greater number of the positively charged directional argon ions 310 reach the bottom 307 of the hole 306. The negative charge at the top 308 of the hole 306 is unable to travel through the isolation dielectric layer 304 to neutralize the positive charge at the bottom 307 of the hole 306. As a result, an excess of positive charge develops in the bottom 307 of the hole 306.
The local electrical potential built-up by the unbalanced distribution of charges at the top 308 and bottom 307 of the hole 306 may degrade the gate oxide 302. The accumulated charge in the bottom of via hole 306 may be carried through the gate 302 to the gate/gate oxide interface (not shown in FIG. 3). Typical gate oxides include native defects at the substrate/oxide interface and in the body of the gate oxide. These defects do not cause a problem in normal circumstances, however, an accumulation of a large amount of charge of one polarity adjacent to the gate oxide 302, such as occurs with conventional RF sputter cleaning of contact holes, causes migration of these defects which can lead to degradation of the integrity of the gate oxide and ultimately to its failure. Such problems may also be caused in the cleaning of via holes where accumulated charge may flow from the bottom of the via hole through the underlying metal layer and contact to the gate and gate oxide, for example in the wafer structure show in FIG. 2.
Accordingly, a RF sputter clean process which does not produce an unbalanced charge distribution in contact and via holes would be desirable.